The present invention generally relates to the field of random pattern creation, trusted supply chain applications, as well as pattern identifier creation and detection across a variety of structures including charge storage devices, data storage and communication systems. In particular, an embodiment can include a non-volatile floating gate charge storage device manufactured and used in accordance with exemplary method(s) of manufacturing which could include a non-volatile floating gate charge storage device.
In the fields of trusted electronics, trusted supply chain management, as well as the field of data storage and communication systems, users are concerned about security and ensuring their devices have not been tampered with. Devices that are sometimes used in this field include anti-tampering devices, unique identification devices, random number generators, cryptographic devices, etc. However, there continues to be a need for a new capability or functions associated with creation of a trusted electronics or trusted supply chain solutions such as devices with irreproducible or a physically uncloneable identification scheme or function. In other words, an aspect of an embodiment of the invention provides a function or effect to be generated that does not allow for another user, e.g., an unauthorized user, to physically clone, copy, or reproduce an original structure manufactured in accordance with an embodiment of the invention.
According to an illustrative embodiment of the present disclosure, a block of floating gate transistors can be provided and manufactured with a unique structure or pattern. A floating gate transistor within a block of floating gate transistors can comprise a semiconductor substrate region, a source region and a drain region separated by a semiconductor substrate region, and a floating gate region having first and second portions. The first portion can be dielectrically separated from the source region, the drain region, and the semiconductor substrate region by a tunnel oxide region. The second portion can be dielectrically separated from a control gate region by an oxide-nitrite-oxide region. At least a portion of the block of floating gate transistors can be subjected to a structure altering stress, e.g., irradiated with heavy ion radiation, to create passage regions in tunnel oxide regions in a random number of floating gate transistors within the block of floating gate transistors. Stress created passage regions can permit at least a portion of an amount of charge to pass from the floating gate region, through the tunnel oxide region, and to the semiconductor substrate region when a random number of floating gate transistors within the block of floating gate transistors are in a non-powered state.
Another aspect of the invention can include a detection scheme using structure that has been formed in accordance with an embodiment of the invention. For example, a first step can include providing a block or array of floating gate transistors, such as described above, that have been subjected to a stress in accordance with an embodiment of the invention that generate alterations in a random number of the floating gate transistors in the block or array subjected to the stress. Next, a detection process adapted to detect an embodiment of a structure manufactured in accordance with an embodiment of the invention can be employed that can include applying an electrical bias in at least one of the semiconductor substrate regions of the block of stressed floating gate transistors that induces a tunneling effect, the tunneling effect causing an amount of charge to gather on associated floating gate regions. Some or all of the gathered charge on the exemplary floating gate regions of the random number of floating gate transistors with the passage regions passes from at least one of the associated floating gate regions, through at least one of said tunnel oxide regions, and to at least one of the semiconductor substrate regions when the random number of the floating gate transistors within the block of floating gate transistors are in a non-powered state. In this example, the amount of charge that passes through the passage regions will vary between ones of the random number of floating gate transistors where some charge amount will range from all of the charge accumulated in the random number of floating gate regions to some of the charge in ones of the random floating gate regions. A detectable, irreproducible, and re-emerging pattern will be formed by the random number of floating gate transistors who each have a different retained charge. This pattern can be overwritten by writing to the random floating gate regions however this pattern will reemerge based on charge loss in random stress altered floating gate transistors. Other embodiments can include taking measurements at specific points in time to determine different charge states of stress altered floating gate arrays at different points of time. Stress alterations can also be done at different points of time or in different points of a supply chain to create different stress alteration patterns at different points of time or in different points in a supply chain movement.
Embodiments can also include a variant which has error correction software or circuits which can selectively deactivate stress altered charge storage devices or electrical circuits where such stress alterations alter such devices or circuits to the point where they are unusable for their intended purpose. Other embodiments can include systems which can detect unauthorized or counterfeit components by comparing component detected stress altered components and comparing them with patterns stored associated with identification codes or names of a stress altered part after biasing the devices or circuits, waiting a predetermined time, and measuring the stress altered components or devices to determine if they match the stored pattern.
Another embodiment can use this system to generate random numbers by inducing stress in an array of charge storage devices resulting in alternation of random array elements. A next step can include reading out the randomly altered array components to generate a random number. Stress sources, such as radiation sources, can generate random alterations in devices or circuits, such as charge storage devices, that cannot be reproduced given a random nature of radiation source exposure.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment exemplifying the best mode of carrying out the invention as presently perceived.